Are you an ASIC DFT engineer with 8+ years experience developing test for high volume mass production chips? Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things? Keen to make a real difference in a VC-backed startup and work in a dynamic & fun environment? Then join Australia’s fastest growing semiconductor company based in Sydney. You’ll work with the team that invented Wi-Fi 20 years ago, and help shape the future of Wi-Fi.

We are open to sponsoring a work visa for the right candidate.

Responsibilities include:

• Chip top DFT architecture and insertion
• Propose and implement design-for-test structures
• Ensure industry-standard scan testability (stuck-at, at-speed, compression)
• Ensure thorough memory BIST solutions
• Deliver DFT into complex, fast-paced ASIC developments
• Ensure implementability via synthesis, design integrity with equivalence checks
• Generate and validate ATPG patterns
• Deliver ATPG patterns to silicon test team, support pattern bringup on tester
• Support silicon production fallout analysis

What we’re looking for:

• 8+ years relevant industry experience
• MSc in Electrical / Electronics / Communication Engineering or Computer Science
• A deep understanding of design for test (DFT) fundamentals
• Complete ASIC DFT system architecture and implementation proficiency
• Experience ensuring industry-best logic test coverage with synthesis-time inserted scan testability, at-speed clock control solutions
• Experience with MBIST insertion and validation prior to tapeout
• Experience with pattern generation (ATPG) for simulation and production
• Experience validating scan and MBIST implementations in SDF-annotated gatelevel simulations, providing sign-off for tapeout
• Experience working with silicon test and operations teams to run fallout analysis and root-cause failures
• Expert with digital simulation environments
• Experience in HDL languages such as Verilog, SystemVerilog or VHDL 
• Experience with building testbench infrastructures
• Experience generating initialization sequences to prepare chip for various test modes
• Experience running and debugging gate level simulations in post-PnR netlists with SDF annotation, power-aware simulation experience is a plus
• Experience with JTAG, SDIO, SPI protocols
• Hands-on experience with Linux development environment staples such as make, shell scripts and Python
• Experience using the git revision control tool

Check out what it is like to work for us:

What we offer:

• Competitive salary + excellent stock option package
• Potential to sponsor a work visa for the right candidate
• Healthy work environment with sit/stand desks and large screens
• Office perks such as stocked drinks fridge, snack bar and barista coffee
• Newly fitted-out offices, with a relaxed, friendly work environment

Who we are:

Morse Micro is Australia’s largest semiconductor company  building Wi-Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to work hard, innovate & invent. Together, we are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney & Picton (Australia), Irvine & Boston (USA), Bangalore (India), Cambridge (UK) and Hangzhou (China).

If you are interested in building the first 802.11ah chipset together with the inventors of Wi-Fi, then send us your resume and application letter to [email protected] and tell us why you should become Morse Micro's ASIC DFT Engineer.

A note to recruitment agencies - We do not accept unsolicited agency resumes and we are not responsible for any fees related to unsolicited resumes.